Úvod do Verilogu

  • case sensitive
  • Klicova slova jsou lowercase
  • stradnik ukoncuje prikaz

Základní struktury

zakladni struktura modulu:

module modulename(portlist);
  port declarations
  datatype declarations
  circuit functionality
  timing spec

endmodule

Komentare

/* komentar */

/* viceradkovy 
komentar*/

// komentar

Ciselne konstanty

Are sized or unsized: <size>'<base format><number>

  • Sized example: 3'b010 = 3-bit wide binary number, The prefix (3) indicates the size of number
  • Unsized example: 123 = 32-bit wide decimal number by default

Defaults:

  • No specified <base format> defaults to decimal
  • No specified <size> defaults to 32-bit wide number

Base Format:

  • Decimal ('d or 'D) 16'd255 = 16-bit wide decimal number
  • Hexadecimal ('h or 'H) 8'h9a = 8-bit wide hexadecimal number
  • Binary ('b or 'B) 'b1010 = 32-bit wide binary numer
  • Octal ('o or 'O) 'o21 = 32-bit wide octal number

Negative numbers - specified by putting a minus sign before the <size>

  • Legal: -8'd3 = 8-bit negative number stored as 2's complement of 3
  • Illegal: 4'd-2 = ERROR!!

Special Number Characters:

  • '_' (underscore): used for readability. Example: 32'h21_65_bc_fe = 32-bit hexadecimal number
  • 'x' or 'X' (unknown value). Example: 12'h12x = 12-bit hexadecimal number; LSBs unknown
  • 'z' or 'Z' (high impedance value). Example: 1'bz = 1-bit high impedance number

Ciselne Operace

Aritmetika:

  • plus +, minus-, nasobeni *, deleni /, modulo %
  • pokud je vstup nedefinovany ci hi-impedance, vysledek je nedefinovany
  • pripadny prenos z nejvyssiho bitu vysledku se ztraci

Bitove operace:

  • and &, or |, negace ~, xor ^, nxor ~^ nebo ^~

Redukcni operatory:

  • ain = 5'b10101, bin = 4'b0011 cin = 3'bZ00, din = 3'bX011
  • & – And all bits – &ain = 1'b0, &din = 1'b0
  • ~& – Nand all bits – ~&ain = 1'b1
  • | – Or all bits – |ain = 1'b1, |cin = 1'bX
  • ~| – Nor all bits – ~|ain = 1'b0
  • ^ – Xor all bits – ^ain = 1'b1
  • ~^ or ^~ – Xnor all bits – ~^ain = 1'b0
  • aplikuje se na vsechny bity operandu, vraci 0/1

Porovnani

  • >, <, >=, ⇐
  • (ne)rovnost - ==, !=
  • (ne)rovnost vcetne himp/undex - ===, !==
  • vraci 0/1

Logicke operace

  • and &&, or ||, not !
  • bitovy posun «, »
    • doplnovano nulami, na druhe strane se bity ztraci

Ostatni sajrajt

  • ?: – Conditional – (condition) ? true_val : false_val;
  • { } – Concatenate – ain = 3'b010, bin = 4'b1100; {ain,bin} results 7'b0101100
  • hw – Replicate – {3{2'b10}} results 6'b101010

Priorita

  • + , - , ! , ~ (unary) nejvyssi priorita
  • + , - (Binary)
  • « , »
  • < , > , ⇐ , >=
  • == , !=
  • &
  • ^ , ^~ or ~^
  • |
  • &&
  • ||
  • ?: (ternary)

Prirazeni

Definice symbolicke konstanty:

parameter size = 8;

Definice 8bitoveho registru:

reg [7:0] tmp;

Prubezne prirazeni:

wire adder_out = mult_out + out

nebo

wire adder_out;
assign adder_out = mult_out + out

Prirazeni:

  • blokujici =
  • neblokujici ⇐

Ridici struktury

if .. else

always @(sela or selb or a or b or c)
	begin
     		if (sela)
			q = a;
     		else 
		if (selb)
			q = b;
     		else 
			q = c;
       	end

case

always @(sel or a or b or c or d)
     begin
     	case (sel)
		2'b00 : q = a;
		2'b01 : q = b;
		2'b10 : q = c;
		default :q = d;
       	endcase
      end

casez, casex

casez (encoder)
	4'b1???  :  high_lvl = 3;
	4'b01??  :  high_lvl = 2;
	4'b001?  :  high_lvl = 1;
	4'b0001  :  high_lvl = 0;
	default    :  high_lvl = 0;
endcase	

casex (encoder)
	4'b1xxx  :  high_lvl = 3;
	4'b01xx  :  high_lvl = 2;
	4'b001x  :  high_lvl = 1;
	4'b0001  :  high_lvl = 0;
	default    :  high_lvl = 0;
endcase	

forever – cykli donekonecna

initial 
begin
  clk = 0;
  forever  #25  clk = ~clk;
end

repeat – cykli prave x-krat

repeat (8)
begin
    tmp = data[15];
    data = {data << 1, temp};
end

while – podmineny cyklus

while (count < 101)
    begin
	$display (&#8220;Count = %d&#8221;, count);
	count = count + 1;
    end

for

for (i = 4; i <= 7; i = i + 1)
	begin
	    result[i] = result[i-4];
	end

Fcni bloky

Inicializacni blok

  initial
      begin
  	b = 1'b1;
         #5 	c = 1'b0;
         #10 	d = 1'b0;
      end

User defined primitives

primitive latch (q, clock,data); // Level sensitive, active low
output q;
reg q;
input clock, data;
initial q = 1'b0; // Output is initialized to 1'b0.
		   // Change 1'b0 to 1'b1 for power up Preset
table
	// clock data current state next state
	      0        1          :?:            1;
	      0        0          :?:            0;
	      1        ?          :?:            -; // '-' = no change
endtable
endprimitive

Příklady

always @(a or b or c or d or sel)
  begin
    case (sel)
   	2'b00: mux_out = a;
	2b'01: mux_out = b;
	2b'10: mux_out = c;
	2'b11: mux_out = d;
    endcase
module mult_acc (out, ina, inb, clk, clr);

input [7:0] ina, inb;
input clk, clr;
output [15:0] out;

wire [15:0] mult_out, adder_out;
reg [15:0] out;

parameter set = 10;
parameter hld = 20;
assign adder_out = mult_out + out;

always @ (posedge clk or posedge clr)
   begin 
	if (clr) 
		out = 16'h0000;
	else 
		out = adder_out;
   end 

multa u1(.in_a(ina), .in_b(inb), .m_out(mult_out));

specify 
	$setup (ina, posedge clk, set);
	$hold (posedge clk, ina, hld);
	$setup (inb, posedge clk, set);
	$hold (posedge clk, inb, hld);
endspecify
		
endmodule
 
hw/verilog.txt · Poslední úprava: 2006/09/08 19:20 (upraveno mimo DokuWiki)

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